Cadence launches industry's first level-5 autonomous AI agent for semiconductor design

Cadence, the semiconductor design software company, has unveiled what it calls the semiconductor industry's first fully autonomous virtual AI design engineer, extending its ChipStack AI Super Agent framework to Level-5 autonomy and marking a new step in the adoption of agentic artificial intelligence across chip development workflows. Announced at COMPUTEX 2026, the new system combines Cadence's electronic design automation (EDA) software portfolio with NVIDIA Nemotron models and NVIDIA OpenShell runtime to automate complex chip design and verification tasks. The company said the platform can significantly reduce validation timelines by enabling engineers to run hundreds of simulations and verification workflows autonomously. According to Cadence, the technology can accelerate register-transfer level (RTL) validation cycles by more than 40 times, reducing a verification process that traditionally takes around five weeks to less than a day. The company noted that NVIDIA engineers collectively run millions of verification tests and consume billions of compute hours annually as part of semiconductor development. From AI assistant to autonomous engineer The latest version of ChipStack moves beyond AI-assisted engineering by allowing the platform to independently execute design and verification workflows while keeping human engineers involved for supervision and guidance. Rather than relying on step-by-step prompts, the system evaluates intermediate results, determines subsequent actions, and iterates toward design completion. The platform can handle tasks including specification analysis, RTL generation, verification planning, formal analysis, simulation, debugging, and design convergence. Paul Cunningham, Senior Vice-President and General Manager of the System Verification Group at Cadence, said customers are increasingly using AI to help engineering teams tackle more complex semiconductor projects. "We're taking the next step—moving from AI that assists engineers to autonomous virtual engineers that can implement real design and verification work," he said. Security and Governance A key element of the announcement is the integration of NVIDIA OpenShell, a sandboxed runtime environment designed for autonomous AI agents. Cadence said the runtime provides governance controls, isolation mechanisms, and managed access to tools and infrastructure, helping organizations protect sensitive intellectual property and design data while deploying autonomous AI systems in production environments. The company said its physics-based design and verification engines help ensure AI-generated outputs remain grounded in signoff-accurate engineering models. Timothy Costa, Vice-President and General Manager of Computational Engineering at NVIDIA, said engineering teams require AI systems that accelerate verification without compromising security, trust, or operational control. Expanding its agentic AI portfolio The announcement builds on Cadence's broader strategy around agentic AI following its acquisition of ChipStack in November 2025. Since then, the company has introduced multiple AI-focused products, including ViraStack AI Super Agent for analog and custom design, InnoStack AI Super Agent for digital implementation and signoff, and AgentStack, an orchestration framework for coordinating AI-driven engineering workflows. The latest release extends those capabilities into fully autonomous operation, reflecting a wider industry trend toward AI agents capable of executing specialized engineering tasks with minimal human intervention. Cadence said the Level-5 autonomous capabilities of the ChipStack AI Super Agent and the AgentStack orchestration framework are expected to be available to early-access customers during the second half of 2026. The launch highlights how agentic AI is moving beyond coding assistants and productivity tools into highly specialized engineering domains. As semiconductor designs become increasingly complex, autonomous AI systems capable of handling verification and validation workflows could play a growing role in reducing development timelines and improving engineering efficiency across the chip industry.